The present invention relates to a method of designing cells applicable to different design automation (DA) systems, a method of fabricating a semiconductor integrated circuit using a cell library developed by the particular cell-designing method, and a technique effectively applicable to the designing of a basic cell utilized for, for example, the standard cell system.
In an automatic placing and routing system for fabricating a semiconductor integrated circuit device (hereinafter sometimes referred to simply as "LSI device"), cells are placed and routed between terminals on a semiconductor substrate. The cells include basic cells of a standard cell system or a cell-based system, and are registered in a library as a functional block of, for example, a flip-flop or a two-input NAND gate. The layout of these cells is prepared through an automatic cell layout preparation program on the basis of a circuit diagram designed in advance. This automatic cell layout preparation program is for generating an actual cell pattern on the basis of circuit diagram information, a layout rule on the fabrication process of the LSI device and performance designating information such as the width and length (W/L) of the transistor.
Design automation (DA) systems for automatic placing and routing of basic cells include those marketed by various computer-aided design (CAD) system makers and those internally fabricated by semiconductor integrated circuit device makers. Individual DA systems, however, are required to meet the input/output terminal requirements specific thereto. The input/output requirements constitute conditions to be met for connecting cells to each other and relate to the layout pitch, layout level and the material of the conductors for external connection of cells. In the case where different DA systems are used for the same functional block, for example, as shown in FIG. 1, the input/output conditions are that the minimum layout pitch of the conductor is 2.8 .mu.m with the material and the layout level of the conductor met by a second-layer aluminum conductor AL2 for one DA system, and that the minimum conductor layout pitch is 3.4 .mu.m with the material and layout level of the conductor met by a polysilicon conductor POLS and a second-layer aluminum conductor AL2 for another DA system. Therefore, the input/output terminals requirements of these two materials have nothing in common and are incompatible with each other.
As shown in FIG. 2, the steps for producing a library of basic cells include logic designing 10, circuit designing 11, pattern designing 12, production of a delay library 13, and registration 14 of the data obtained in the foregoing steps. In the logic designing step 10, the kind of gate function to be developed for a cell is studied, and the logics designed to realize the particular function. Generally, substantially the same function of a standard cell is required for different DA systems, and the currently-available logics may be used for the same purpose, thus requiring substantially no designing. The circuit designing step 11 is for designing a circuit to realize a required logics with an MOS transistor, for example. This step may also utilize a currently-available circuit as in the logics designing and requires not so many designing processes. The pattern designing step 12 is for designing a layout for realizing a MOS transistor circuit as a pattern on the wafer. As to the number of designing processes for this step, the redesigning is necessary for each generation of the process used, and the designing of a cell library accounts for a major proportion. Also, different DA systems are required to meet different conditions for connection (input/output terminal requirements) of the cell input/output portions, thus making necessary a pattern designing for each DA system. In the delay library preparation 13, a delay constant is determined by circuit simulation. This step requires designing processes more than the logics designing or circuit designing but less than the pattern designing. In this way, the greatest portion of the designing processes relating to cell library development consists of cell pattern designing required to be developed for each automatic placing and routing system (hereinafter referred to simply as "DA system").
Some DA systems are good at cell placing and routing for fabrication of a large-scale logic circuit device, and other DA systems are suitable for cell placing and routing only for fabricating a small-scale logic circuit device. Still other DA systems are capable of designing an IC (ASIC) for special applications within a short period of time. In many cases, therefore, the same semiconductor maker uses a plurality of DA systems for designing integrated circuits. In such a case, independent development of a standard cell library for each DA system is a double investment of designing resources. The turn-around time for development of the cell library would be lengthened in such a field as ASIC where the important key for creating customers is to develop and supply a cell library to the market as fast as possible.